Perceptia (IP and Design Services) of Scotts Valley, CA, today confirmed functionality and ultra-high performance of its DeepSub™ pPLL01 hard IP core. The pPLL01 has an output frequency ranges from 9 ...
Selection underscores QuickLogic's ability to deliver flexible, silicon-proven IP that reduces ASIC risk and shortens design cycles for commercial applications SAN JOSE, Calif., Nov. 18, 2025 ...
MOUNTAIN VIEW, Calif., July 6, 2004 - MIPS Technologies, Inc. (Nasdaq: MIPS), a leading provider of industry-standard processor architectures and cores for digital consumer and business applications, ...
Visit Hall 6, Stand R19 at Space Tech Expo Europe 2025 to learn more With silicon-proven reliability and export-compliant (EAR99) availability, QuickLogic's eFPGA IP empowers engineers to integrate ...
eFPGA Hard IP Technology: QuickLogic's eFPGA Hard IP provides post-manufacturing design flexibility, enabling developers to modify the functionality of their SoCs to introduce new features, support ...
Having developed IP for fabrication processes and Hard IP Core designs lowers customer risks, shortens our development and revenue recognition cycles, and provides us with favorable financial leverage ...
SAN JOSE, Calif. & BLOOMINGTON, Minn.--(BUSINESS WIRE)--QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP and Endpoint AI solutions, ...
The integration of “hard” intellectual property blocks–those delivered as GDSII databases–lets system designers focus on their core competency by outsourcing certain blocks that previously had to be ...
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