CORRECTING and REPLACING Panmnesia Supplies PCIe 6.4--CXL 3.2 Fusion Switch Sample Chip

Panmnesia's PCIe 6.4-CXL 3.2 Fusion Switch Sample. The updated release reads: PANMNESIA SUPPLIES PCIe 6.4--CXL 3.2 FUSION SWITCH SAMPLE CHIP. World's Only ASIC Switch Chip with Po ...
TMCnet

Panmnesia to Mass-Produce PCIe 6.4-CXL 3.2 Fusion Fabric Switch

Panmnesia (CEO Myoungsoo Jung), a South Korean fabless company developing link solutions for AI infrastructure, announced ...
Semiconductor Engineering

PCIe 8.0: Enabling The Next Generation Of High Bandwidth Systems

As data rates continue to increase, maintaining reliable links requires careful coordination between the PHY and controller ...
EDN

PCIe switch features next-gen architecture

The PEX 8517 PCIe switch IC has a streamlined second-generation switching architecture with five ports and 16 lanes. The device features 150-ns latency, improved throughput, reduced per-port costs, ...
Nasdaq

Cadence Achieves PCIe 5.0 Specification Compliance for PHY and Controller IP in TSMC Advanced Technologies

SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its PHY and Controller IP for the PCI Express® (PCIe®) 5.0 specification in the TSMC N7, N6 and N5 ...
Morning Overview on MSN

Samsung readies PCIe 5.0 QLC SSD with a RISC-V based controller

Samsung is preparing a PCIe 5.0 SSD that pairs quad-level cell (QLC) flash memory with a RISC-V-based controller, a combination that could reshape cost and performance expectations for storage in ...
Semiconductor Engineering

PCIe 7.0 Takes Center Stage At PCI-SIG DevCon ’24

As accelerated computing goes mainstream, PCIe links are poised to take on a role of higher importance in systems. June 13th, 2024 - By: Gautam S. From the simplest building blocks like GPIOs to the ...
ExtremeTech

Leak: Intel's Rocket Lake To Deliver New 14nm CPU Architecture, PCIe 4.0

Intel's Rocket Lake could deliver the largest uplift in chipset capabilities that we've seen in quite some time -- as well as a new CPU architecture despite the fact that RLK is still a 14nm part.
Nasdaq

Astera Labs First to Demonstrate End-to-End PCIe over Optics for GPU Clusters Across the Data Center

Company extends its PCIe connectivity leadership to increase GPU cluster scale and utilization in disaggregated AI and cloud infrastructure SANTA CLARA, Calif.--(BUSINESS WIRE)-- Astera Labs (Nasdaq: ...
Business Wire

Astera Labs First to Demonstrate End-to-End PCIe over Optics for GPU Clusters Across the Data Center

SANTA CLARA, Calif.--(BUSINESS WIRE)--Astera Labs (Nasdaq: ALAB), a global leader in semiconductor-based connectivity solutions for AI and cloud infrastructure, today unveiled the industry’s first ...