EDN

A SystemC-based UVM verification infrastructure

My company, TVS, recently completed a SystemC-based Universal Verification Methodology (UVM) project for Blu Wireless Technology, a UK-based company that develops silicon-proven mmWave wireless ...
Design-Reuse

Mentor Graphics Extends UVM Connect to Support OVM

WILSONVILLE, Ore., September 10, 2012 — Mentor Graphics Corporation (NASDAQ: MENT) today announced availability of an update to the popular Universal Verification Methodology Connect (UVM Connect) ...
Business Wire

Aldec’s Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
Design-Reuse

Easier UVM Sequences - SystemVerilog UVM Sequence and Task Equivalence

SystemVerilog [1] UVM [2] sequences [4][5] are a powerful way to model stimulus and response for functional verification. Unfortunately using SystemVerilog UVM sequences can require an extensive ...
EDN

Hardware-assisted verification, from its dawn to SystemVerilog, UVM, and transactors

My [LR’s] first exposure to hardware emulation happened circa 1995 upon visiting a major processor firm in Austin, Texas. Its lab was jam-packed from floor to ceiling with monstrous hardware emulators ...
Design-Reuse

SystemC Verification, Simulation & Emulation of Secure Digital IP

This paper describes the process and tools used in the verification of a family of Secure Digital (SD) IP cores. The verification process described included SystemC verification, RTL simulation and ...
EDN

New simulation capabilities advance SystemVerilog

Santa Cruz, Calif. — Two verification providers — Mentor Graphics Corp. and Axiom Design Automation — are claiming new simulation technology this week that offers broad support for the emerging ...
EDN

Design patterns in SystemVerilog OOP for UVM verification

SystemVerilog supports templates for generic code writing using parameterized classes. Here we’re going to describe some of the design patterns in the code that make up the UVM base class library.
Semiconductor Engineering

Extending UVM To Analog

Analog/mixed-signal content in SoCs needs to be modeled in a similar way as the digital content but does UVM make sense for pure analog? Perhaps not. As SoC complexity has grown, so too has the need ...
EDN

SystemC seen accelerating simulation

SAN JOSE, Calif. — SystemC is seeing increasing use as a way of accelerating simulation, according to speakers at the DVCon Design and Verification Conference. Meanwhile, speakers noted important ...
EDN

Aldec claims Verilog simulation speedup

HENDERSON, Nev. — For most IC designers, logic simulation can never be fast enough. Aldec Corp. is paying attention, and is claiming that its new Riviera-Pro 2006.10 HDL simulator provides a 57 ...
Design-Reuse

Aldec's Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

Henderson, USA – December 3, 2019 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...